• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    It comprises several processing units, a priority allocation network (BSAUOK-BSIUOK, BSMYOK) to which each of these units is connected, and an omnibus line linking all the units in order to provide communication between any two of them. The apparatus is provided to enable each unit, concurrently with other units, to communicate with another via the omnibus line and at a speed depending on the sending unit itself and not on the limits imposed on all the communications. In order to determine, at any instant, which among several units simultaneously seeking to set up a communication, should have the priority, each unit comprises priority-determining circuits (Fig.) inserted into the said network according to a sequence which determines their relative priorities for the communications. Each circuit comprises means (15, 17, 18) for indicating that the unit in question requires communication with another unit, as well as means (19, 22, 23) allowing asynchronous transfer of information by this unit, via the omnibus line (10), when no unit having a higher priority is transmitting information nor is attempting to transmit it. <IMAGE>
    公开号:SU1274634A3
    申请号:SU762378195
    申请日:1976-06-29
    公开日:1986-11-30
    发明作者:Дж.Барлоу Джордж；В.Кассарино Фрэнк (Младший)；Б.Оъкиф Дэвид；Дж.Бикэмпис Джорж；В.Конвей Джон；А.Лимей Ричард；Л.Риконен Дуглас；В.Вудс Вильям
    申请人:Ханивелл Информейшн Системз Инк (Фирма)；
    IPC主号:
    专利说明:

    The device relates to data processing systems, in particular to a data processing process carried out on a common I / O bus. The aim of the invention is to increase speed. The drawing shows a diagram of the device. The circuit contains bus 1 Bus request, bus 2 Start of data cycle, priority pin group 3 trunk, strobe output 4 devices NOT elements 5-8, AND elements 9, 10, AND-NE elements 11, 12, ORINE elements 13-17, delay elements 18, 19, query triggers 20 and 21, resolution trigger 22. Tires Confirmation 23, Standby 24, No confirmation 25, system reset input 26, request input 27, output 28. The device operates as follows. In the initial state, there is no cycle of the priority scheme and the bus request signal on bus 1 has a binary level I. When this bus request signal is equal to binary l, then the output of the NOT 5 element will be the binary O level. The output of the HE 5 element is connected to one of the inputs of the AND 9 element, the other inputs of which receive a 1 pin clear signal, which is normally equal to binary 1, and the output signal of the element OR NOT 13, to The second signal is also normally equal to two-bit one. Therefore, the output signal of the AND 9 element is a binary O when the bus is in the initial state, and therefore the output of the element of the holder 19 is binary O. The presence of the binary O at the input and: the output of the element 19, the delay determines the soup (declaring a binary 1 at the output of an OR-NOT element. When one of the devices connected to the bus requires a bus cycle, it sets its trigger 20 asynchronously, so that binary output appears at its output. Thus if the tire is in its original state ns, the lane howling effect, which occurs at the transition tire operating state, is to install ISTO .nikom trigger information 20 lock the belt. If both inputs of the NANDI element 11 are in the state of binary 1, then at its output a binary O is used at the same time. As a result, a request trigger 21 is set, so binary 1 is output at its single output. Consequently, at a single output of trigger 21 the request is asynchronously set to binary 1. The state of binary 1 of the signal from the single output of trigger 21 enters it 1 in the transformed form through the element NOT 7 as binary O. Any request to the system from any of the triggers 21 queries various devices connected to the bus will not maintain a binary O state on the bus. Delay element 19 introduces sufficient delay to compensate for propagation delays introduced by elements 14, 11 and trigger 21. Thus, even if a request trigger 21 is installed in the device, this does not mean that a device with a higher priority, which also requests a bus cycle, will not receive the next bus cycle for itself. For example, if a device with a lower priority sets its request trigger 21, a binary O signal is sent to all devices, including a device with a higher priority, which in turn generates a binary 1 state at the output of its element AND 9 and binary O at the output of the element OR NOT 14, thereby prohibiting the installation of the trigger 21 of the request of another similar device with a higher priority, if the trigger 20 of another device with a higher priority has not yet been set. If the delay was, for example, about 20 NS, and at the output of the delay element 19 of another device with a higher priority a binary 1 state was established, then the output of the OR-NO 14 element will be a binary O state, so that whether or not trigger 20 of another device with a higher priority is set, the output signal of the NAND element will be binary 1, preventing the trigger trigger 21 from being installed. Thus, at this time, all devices will have their triggers 21 requests set, if they requested service, as indicated by the installation
    their trigger 20. After the delay time provided by the device element 19, which first requested the pin cycle, the device has not yet established its request trigger 21, can not do this until the bus cycle ends. As a result, a device with a higher priority may capture the bus, even if its trigger 20 is set to a lower priority.
    Thus, all the triggers 2 of the request for devices requesting a bus cycle will be set during such an interval, which is determined by the deceleration element 19. Despite the fact that many devices connected to the bus can set up their own request triggers 21 during the specified time interval, only one of these devices will set its trigger level 22. The device installed with the resolution trigger 22 will be the device having the highest priority and requesting the bus cycle. When this device has completed its operation during its bus cycle, other devices with query triggers 21 set again to resume the requirements for the next such cycle of titanium, etc. Therefore, the signal of the single output of the request trigger 21 is not only fed to the NOT 7 element, but also goes to one of the inputs of the AND-NO element 12. The zero output of the trigger 21 is connected to one input of the AND 10 element. The input signals to the IEE 12 element arrive at the device higher priorities, and in particular, for example, from nine prior devices with higher priority (signals from a bus group .3). If one of these nine signals has a binary O level, this will mean that the device with a higher priority has requested a bus cycle, as a result of which the device in question is not allowed to install its enable trigger 22, which will make it impossible for the device to get the next bus cycle.
    Other input signals received by the element AND-NOT 12, come from the output of the delay element 19 and from the output of the element OR NOT 17. The output signal of the delay element 19 is represented by 746344
    is a binary 1, if at all other inputs of the element AND-NO 12 is also binary 1, this will result in the installation of a trigger 22 5 resolution. The input signal coming from the element OR-NOT 17 has a binary level of 1 when the bus is in the initial state. The inputs of the element OR-NOT 17 are given 0 signals Confirmation, Wait, No acknowledgment, System reset. If one of these signals has a binary level of 1, then the bus, respectively
    5 will be in working condition and it will not be possible to set trigger 22.
    If trigger 22 is set, then its output signal is equal to binary 1 and is inverted into a signal with
    0 is a binary O level using the HE element 8, which then goes to bus 2. This completes the bus cycle priority cycle.
    In addition, if considered
    5, the device is maintenance free and is the device with the highest priority, then the two input signals received by the NAND element 12 from the delay element 19 and the higher priority bus will have the level
    0 binary 1. However, the zero output of flip-flop 21 will be in the binary O state, as a result of which in the binary O state there will be a signal at the output 28, indicating the device with lower priority following it, as well as other devices with lower priority that there is a requesting device with a higher priority that will use the following bus cycle. These very lower priority devices are prohibited from using the next bus cycle.
    5. After completion of the priority cycle, the binary O state on bus 2 appears. This leads to the generation of the binary 1 state at the output of the NOT 6 element and the binary O status at the output of the OR-NOT 13 element, due to which the AND element 9 cannot generate the state of binary 1. In addition, the state of binary 1 at the output of the HE element 6
    权利要求:
    Claims (1)
    [1]
    5 arrives at a delay element 18, the delay time of which, for example, is 60 n. The output signal from the delay element 18 is also fed to another input of the OR-NOT 13 element in order to continue the prohibition of the AND 9 element during the gate generation. Therefore, at the end of the delay period set by delay element 18, a strobe signal is generated at output 4. Thus, a period 60 not created by delay element 18 prohibits the operation of the device, which allows the device with the highest priority that issued the request without interference use the next cycle pins. The strobe generated at the output of the delay element 18 is used by the potential slave device as a synchronization signal. If the strobe signal was transmitted, one of the devices acting as a slave will answer in one of the Confirmation, Waiting or No acknowledgment signals, which are received at one of the inputs of the element OR NOT 17. If it is received, for example, Acknowledgment signal (input 23) or any of these response signals, this will reset the enable trigger 22. The logical equivalent of the Confirmation signal, as well as the other two signals, is received by the element OR NOT 16. These signals differ only by a delay of a few nanoseconds. This causes the trigger 21 to reset. The Confirmation signal and the other two signals will only be received The device and only in this device the request trigger 21 and the trigger 20 are reset. The trigger 20 will be reset to the initial state through the element OR NOT 15, if the trigger resolution 22 is set to one, or if the signal of the fflogo reset is received. Thus, this process is continued in an asynchronous manner for each device, so that one of the information points connected to the bus can use the next bus cycle. A device for prioritizing the connection of a source of information to a common highway containing request triggers, delay elements, NOT, NAND, NOR, NONE, AND, a resolution trigger, characterized in that, in order to improve speed, it has first and The second element is NOT connected to the Zai bus. The beginning of the cycle is the data of the trunk source, the output of the first element is NOT connected to the first input of the first element I, the second input of which is connected to the system reset input of the device, and the third input is connected to the output of the first unit ORENT NOT, the first and second inputs of which directly and through the first delay element are connected to the output of the second element, the output of the first delay element is the gate output of the device, the output of the first AND element directly and through the second delay element is connected respectively to the first and second inputs the second element OR NOT, the output of which is connected to the first input of the first NAND element, the second input of which is connected to the single output of the first query trigger, the single input of which is connected to the bus the source of information sources, and the zero input through the third element OR — NOT is connected to the bus signal of the trunk gating and the system reset input of the device; the output of the first AND element is connected to the single input of the second request trigger, the zero input of which through the fourth element OR is NOT connected to National confirmation, no confirmation of the source of information and the system reset input of the device, the unit output of the second request trigger is connected to the first input of the second NAND to via the third element NO, from the buses The request of the trunk's origin, the zero output of the second trigger of the request is connected to the first input of the second element AND, the second and third inputs of which are connected respectively to the output of the second delay element and NINA of the highest priority of the highway, the input group of the second element AND NOT is connected to the priority bus group of the trunk and the output is connected to the single input of the enable trigger:, zero input. which is connected to the second input of the second element AND-NOT and through the fifth element OR-NOT with wheat Acknowledgment, Waiting, Lack sub 7127463A8
    confirmation of the information source and the Rala and with the first input of the third elevator of the system reset of the device, OR OR NOT, the output of the second element, the single output of the resolution trigger is connected to the corresponding through the fourth element NOT connected by the priority bus of the master level of the beginning of the data cycle of the highway.
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    同族专利:
    公开号 | 公开日
    CH613061A5|1979-08-31|
    SE420360B|1981-09-28|
    NL188920C|1992-11-02|
    HK37180A|1980-07-18|
    GB1541276A|1979-02-28|
    SE7607421L|1976-12-31|
    DE2629401C2|1989-01-19|
    NL7607167A|1977-01-03|
    DE2629401A1|1977-01-20|
    FR2316660B1|1983-05-13|
    FR2316660A1|1977-01-28|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US3815099A|1970-04-01|1974-06-04|Digital Equipment Corp|Data processing system|
    US3676860A|1970-12-28|1972-07-11|Ibm|Interactive tie-breaking system|
    US3832692A|1972-06-27|1974-08-27|Honeywell Inf Systems|Priority network for devices coupled by a multi-line bus|
    US3866181A|1972-12-26|1975-02-11|Honeywell Inf Systems|Interrupt sequencing control apparatus|
    US3886524A|1973-10-18|1975-05-27|Texas Instruments Inc|Asynchronous communication bus|US4074353A|1976-05-24|1978-02-14|Honeywell Information Systems Inc.|Trap mechanism for a data processing system|
    CA1120123A|1976-11-11|1982-03-16|Richard P. Kelly|Automatic data steering and data formatting mechanism|
    ES474428A1|1977-10-25|1979-04-16|Digital Equipment Corp|A data processing system incorporating a bus|
    GB2076191B|1978-12-26|1983-06-02|Honeywell Inf Systems|Improvements in or relating to terminal systems for data processors|
    FR2474198B1|1980-01-21|1986-05-16|Bull Sa|DEVICE FOR DECENTRALIZING THE MANAGEMENT OF THE DATA TRANSFER BUS COMMON TO SEVERAL UNITS OF AN INFORMATION PROCESSING SYSTEM|
    FR2474199B1|1980-01-21|1986-05-16|Bull Sa|DEVICE FOR OVERLAPPING SUCCESSIVE PHASES OF INFORMATION TRANSFER BETWEEN SEVERAL UNITS OF AN INFORMATION PROCESSING SYSTEM|
    IT1149252B|1980-09-09|1986-12-03|Sits Soc It Telecom Siemens|INPUT-OUTPUT MODULE FOR AN ELECTRONIC PROCESSOR|
    US4724519A|1985-06-28|1988-02-09|Honeywell Information Systems Inc.|Channel number priority assignment apparatus|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US05/591,902|US4030075A|1975-06-30|1975-06-30|Data processing system having distributed priority network|
    US05/591,964|US3993981A|1975-06-30|1975-06-30|Apparatus for processing data transfer requests in a data processing system|
    US05/591,904|US4000485A|1975-06-30|1975-06-30|Data processing system providing locked operation of shared resources|
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